Semiconductor Device Physics & Reconfigurable Hardware Systems
Simulating the transistors that don't exist yet, and building with the ones that do.
About
I am a researcher at BRAC University working at the intersection of semiconductor device physics and hardware-efficient compute architectures. My current research focuses on simulating sub-5 nm multi-bridge-channel transistors (MBCFETs) using Silvaco TCAD, alongside designing reconfigurable, hardware-efficient neural accelerators on FPGA fabric using Vitis HLS.
In addition to device modeling and digital design, I have a strong foundation in aerospace and embedded systems, having previously led the avionics and ground station engineering for a 3U CubeSat mission and developed locomotion and autonomy pipelines for robotic platforms.
Education
Roles & Positions
Research Assistant
Leading hybrid neural-accelerator research with FPGA / HLS prototyping of a reconfigurable compute engine for edge AI, going from a Python model to an AMD Artix-7 bitstream.
Previously
2025
Oct 2024
Research & Engineering Domains
Four core research and development focus areas. Click to explore detailed notes and work.
FPGA & Reconfigurable Computing
- Hardware accelerator design on Artix-7: Vivado HLS to bitstream.
- AXI4-based co-design between custom IP and embedded ARM cores.
- Bridging Python-trained models to Verilog hardware for edge inference.
Semiconductor Device Physics
- Beyond-CMOS: GAA FETs and MBCFETs for next-generation logic.
- Device modeling and electrical simulation in Silvaco TCAD (Atlas).
- Short-channel effects and leakage reduction at deep scaling.
VLSI & IC Design
- RTL design, functional verification, and architecture optimisation.
- PPA-driven design-space exploration for arithmetic units.
- Cadence / Vivado / Synopsys flow integration.
Embedded Systems & Robotics
- Locomotion algorithms for planetary rovers and quadrupeds.
- CubeSat avionics, sensor fusion, and real-time data pipelines.
- Microcontroller integration for resource-constrained platforms.
Active Research
Two open threads: a hardware accelerator targeting edge AI workloads, and a TCAD study of multi-bridge-channel devices for sub-5 nm logic.
Hybrid Neural Accelerator
A reconfigurable LUT / logarithmic compute engine for AI inference, prototyped on the Artix-7 XC7A200T.
- Vivado HLS compute engine optimised for PPA across mixed precisions.
- RTL prototype with timing closure and resource mapping on XC7A200T.
- AXI4-based co-design between custom IP and ARM cores.
MBCFET Modeling
GAA Multi-Bridge-Channel FET simulation in Silvaco TCAD, targeting sub-5 nm technology nodes.
- Analysis of short-channel effects, DIBL and subthreshold behaviour.
- Nanosheet dimension optimisation to maximise Ion/Ioff ratios.
- Electrostatic design-space sweeps across stack geometries.
Engineered Artifacts
CubeSats, payloads, and autonomous platforms, featuring multi-system builds led from concept through hardware integration.
Hybrid Neural Accelerator
Reconfigurable compute engine for AI inference, featuring mode-switching LNS/INT arithmetic prototyped on Artix-7.
MBCFET Modeling
GAA Multi-Bridge-Channel FET simulation in Silvaco TCAD, targeting sub-5 nm technology nodes.
CNN Digit Detector
Full PyTorch-to-FPGA pipeline that trains a 2D CNN on an 8×8 digits dataset, exports fixed-point weights, and displays live recognition over HDMI.
Interactive FPGA Adder
Interactive 4-bit accumulator implemented in Verilog HDL on the PA-StarLite board, featuring debounced button control, a custom dynamic I2C LCD driver, and real-time UART logging.
Sobel Video Co-Processor
Real-time 3×3 convolution video filter in Vitis HLS, streaming at II=1 (one pixel per clock) into a flat-Verilog 720p HDMI pipeline, using 0 DSPs and ~1% of the fabric.
Autonomous Aerial Survey
Autonomous drone pipeline combining flight simulation, image processing, and survey automation.
APSCO CubeSat 3U Mission
End-to-end 3U CubeSat with EPS, OBC, comms, ADCS, antenna and ground station developed through 3D, PCB, and orbital simulation.
BIRDS-X APRS Payload
APRS payload focused on energy-transition messaging. Phase 1 winner of the national BIRDS-X space payload competition.
Publications
Tools in Rotation
The working toolchain, spanning from device simulation at the silicon level up through IC design, PCB, and embedded systems.
Silvaco TCAD
Synopsys Sentaurus
Synopsys HSpice
DEVSIM
Cadence Suite
AMD Vivado
Vitis HLS
Altium Designer
KiCad
SOLIDWORKS
Fusion 360
MATLAB / Simulink
Proteus
LTSpiceAwards & Achievements
Licences & Certifications
Industrial Training
Let's build something.
Open to research collaborations, PhD opportunities, and IC / hardware roles.