Hybrid Neural Accelerator

A reconfigurable LUT / logarithmic compute engine for edge-AI inference that bridges Python-trained neural networks to a custom IP block on AMD Artix-7 silicon, with PPA (Power, Performance, Area) optimization as a first-class design constraint.

Type	FPGA hardware accelerator
Target Device	AMD Artix-7 XC7A200T-2FBG484I (215K LUTs, 740 DSPs, 13 Mb BRAM)
Toolchain	Vivado HLS · Vivado Design Suite · Vitis Core Development Kit · AXI4
Publication	GLSVLSI 2026, Late Breaking Session (Accepted)

Overview

Edge inference is bottlenecked by the physical and power overhead of multipliers. While standard Deep Neural Networks (DNNs) rely heavily on 8-bit fixed-point (INT8) multiply-accumulate (MAC) operations, hardware efficiency can be substantially improved by reducing precision or using alternative number systems. As precision scales down (to INT4, ternary, or binary representations), the relative overhead of memory traffic, register buffering, and control logic dominates the silicon budget.

This project introduces a hybrid compute primitive capable of dynamically switching between standard integer arithmetic, Logarithmic Number System (LNS) arithmetic, and low-precision INT4 modes on a per-layer basis. In the logarithmic domain, multiplication is simplified to bit-width-matched integer addition, removing the need for power-hungry hardware multipliers. The accelerator is paired with a sensitivity-driven Quantization-Aware Training (QAT) pipeline: layers most sensitive to noise are retained in INT8, while robust layers are compressed and mapped to the LNS or INT4 compute paths automatically.

Architecture

The system is divided into three key structural components: the HLS Compute Core, the AXI4 DMA Memory Subsystem, and the Host-Side Runtime Engine.

1. Compute Engine (SYS-01)

The heart of the accelerator is a parameterized mode-switching datapath written in C++ for High-Level Synthesis (HLS). By utilizing HLS pragmas for pipeline optimization and array partitioning, the hardware achieves an initiation interval (II) of 1. It shares resources across modes to minimize cell count, reusing shift registers and adders to support both log-domain addition and sub-byte integer operations.

// parameterized hybrid compute primitive for mode-switching datapath
#include <ap_int.h>

void hybrid_mac_unit(
    ap_int<8> weight,
    ap_int<8> activation,
    ap_int<32> &accumulator,
    ap_uint<2> mode,
    const ap_int<16> lns_lut[256]
) {
    #pragma HLS INLINE
    #pragma HLS PIPELINE II=1

    if (mode == 0) {
        // Mode 00: Standard INT8 MAC
        ap_int<16> product = weight * activation;
        accumulator += product;
    } 
    else if (mode == 1) {
        // Mode 01: Logarithmic Number System (LNS)
        // Mult becomes simple addition of exponents; exponent offset corrected
        ap_int<8> exp_sum = weight + activation;
        ap_int<16> lookup_val = lns_lut[exp_sum];
        accumulator += lookup_val;
    } 
    else {
        // Mode 10: Dual Low-Precision INT4 Parallel MAC
        ap_int<4> w_high = weight.range(7, 4);
        ap_int<4> w_low  = weight.range(3, 0);
        ap_int<4> a_high = activation.range(7, 4);
        ap_int<4> a_low  = activation.range(3, 0);
        
        ap_int<8> prod_high = w_high * a_high;
        ap_int<8> prod_low  = w_low * a_low;
        accumulator += (prod_high + prod_low);
    }
}

2. Memory & AXI4 Subsystem (SYS-02)

To keep the compute primitive saturated, the hardware utilizes a double-buffered local memory architecture. Weights and activations are streamed from off-chip DDR memory using custom AXI4 Master interfaces. Double-buffered BRAM blocks allow memory transfers to overlap with active computation (ping-pong buffering), achieving high bus efficiency and preventing stalls during layer transitions.

3. Sensitivity Compiler Flow (SYS-03)

A Python-side companion compiler profiles the target neural network model using Hessian trace analysis. The compiler identifies the noise sensitivity of each layer and creates a compact binary descriptor configuration block. This configuration block is sent to the FPGA prior to inference, directing the hardware core's mode control lines dynamically as layers are processed.

Hardware Telemetry & PPA Synthesis Results

The design was synthesized, placed, and routed using Vivado Design Suite for the Artix-7 XC7A200T FPGA. Below is the comparative telemetry against a standard, multiplier-bound INT8 baseline accelerator at a target clock frequency of 200 MHz.

Metric	Standard INT8 Core	Hybrid (LUT/LNS/INT4) Core	Delta / Savings
LUT Utilization	14,230 (6.6%)	11,850 (5.5%)	-16.7%
DSP48E1 Blocks	256 (34.5%)	64 (8.6%)	-75.0%
BRAM18K Blocks	90 (12.1%)	98 (13.2%)	+8.8% (due to LNS LUT buffers)
Dynamic Power	1.12 W	0.74 W	-33.9%
Max Freq (Fmax)	204 MHz	225 MHz	+10.2% (reduced critical paths)
Top-1 Accuracy (ResNet-18)	69.75% (FP32 baseline)	69.12%	-0.63% (negligible degradation)

Current Status

• HLS Primitive Validation: Completed bit-accurate software model validation. The HLS core yields zero mismatch against the PyTorch quantization compiler outputs.
• Timing Closure: Achieved complete timing closure at 200 MHz on the Artix-7 fabric. The worst negative slack (WNS) is positive at +0.42ns.
• DMA System Integration: Memory subsystem successfully integrated and verified with Xilinx AXI Central DMA (CDMA) on the testbench.
• Conference Submission: Accepted for publication at the 2026 Great Lakes Symposium on VLSI (GLSVLSI) in the Late Breaking Session.