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Active Domain DOM-03

VLSI & IC Design

Tooling: Cadence · AMD Vivado · Synopsys HSpice Focus: RTL · Architecture · PPA

Turning compute architectures into silicon through RTL design, functional verification, and PPA-driven exploration across the full Cadence, Vivado, and Synopsys flow.

Overview

A clean compute idea is only worth as much as the chip it ends up on. VLSI is the discipline of dragging a high-level architecture through every stage, including RTL, simulation, synthesis, and place-and-route, without losing what made it interesting in the first place.

The work here treats power, performance, and area as design variables, not afterthoughts: arithmetic units reshaped to match precision budgets, datapaths balanced for timing, and every micro-architectural choice justified against the PPA frontier.

Sub-areas

  • RTL Design (SUB-01): Synthesizable Verilog / SystemVerilog for arithmetic blocks, pipelines, and control state machines.
  • Functional Verification (SUB-02): Directed and constrained-random testbenches, golden-reference comparisons, and assertion-based checks.
  • Architecture Optimisation (SUB-03): PPA-driven trade studies across pipeline depth, parallelism, and precision to find the right operating point per workload.
  • Low-Power Design (SUB-04): Clock-gating, operand isolation, and precision-adaptive datapaths for energy-constrained inference.
  • Flow Integration (SUB-05): End-to-end Cadence / Vivado / Synopsys flow from RTL through synthesis to gate-level signoff.
  • Arithmetic Units (SUB-06): Custom adders, multipliers, and approximate primitives, which are the building blocks behind every accelerator.

Active Threads

  • R-01: Accelerator Architecture: The compute core inside the Hybrid Neural Accelerator, featuring LUT / log primitives, AXI4 SoC integration, and PPA sweeps.
  • Industrial Attachment: Neural Semiconductor, covering Cadence operation and software exposure in an industry setting (Sep–Oct 2025).

Toolchain

Cadence Design SuiteIndustry-standard digital flow from RTL through GDS exposure via industrial attachment.
AMD VivadoSynthesis, implementation, and timing analysis on FPGA fabric, acting as the daily prototyping tool.
Synopsys HSpiceMixed-signal and analog verification at the block level.
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