FPGA & Reconfigurable Computing

Programmable hardware as a compute substrate, turning Python-trained neural networks into custom IP blocks that run on Artix-7 silicon through HLS, RTL refinement, and SoC integration.

Overview

Reconfigurable computing sits in a useful gap. ASICs give peak efficiency but commit silicon to one workload; CPUs and GPUs are flexible but pay in joules per inference. FPGAs let you trade between the two, re-fabricating the datapath to match the model in front of you.

The work here is about how to actually close that gap in practice: choosing the right compute primitive (LUT, log-domain, approximate), wrapping it in a clean AXI4 SoC, and pushing it through Vivado without losing timing.

Sub-areas

High-Level Synthesis (SUB-01): Algorithmic descriptions in C/C++ compiled to RTL via Vivado HLS, with pragma-driven optimisation of pipelines, dataflow, and memory partitioning.
RTL Architecture (SUB-02): Hand-tuned Verilog where HLS is insufficient, including clock-domain crossings, FIFO sizing, and pipelined arithmetic for predictable timing.
AXI4 SoC Integration (SUB-03): Memory-mapped AXI4 between custom accelerator IP and embedded ARM cores, featuring DMA-driven activations and bitstream-baked metadata.
PPA Optimisation (SUB-04): Power, performance, and area as first-class design knobs, with Vivado reports parsed into sweep dashboards for repeatable exploration.
Quantisation & Approximate Compute (SUB-05): Sensitivity-driven quantisation pipelines that pick precision per layer.
Verification (SUB-06): Bit-accurate C++ models paired with cocotb testbenches, providing coverage-driven regression on representative DNN slices.

Active Projects

R-01 · Feb 2026 – Present Ongoing

Hybrid Neural Accelerator

Reconfigurable LUT / logarithmic compute engine for edge-AI inference, featuring a mode-switching INT8, LNS, and INT4 datapath prototyped on Artix-7 XC7A200T.

−75% DSP usage vs. standard INT8 baseline.
Timing closure at 225 MHz; WNS +0.42 ns.
Accepted at GLSVLSI 2026 Late Breaking Session.

FPGA HLS LNS Edge AI AXI4

Split-screen HDMI output: a photo raw on the left, live Sobel edge detection on the right

P-06 · Jun 2026 Completed

Sobel Video Co-Processor

Real-time 3×3 convolution video filter (Sobel, sharpen, blur, emboss, threshold) built in Vitis HLS and dropped into a flat-Verilog 720p HDMI pipeline, shown live as a split-screen RAW │ FILTERED view.

II=1 line-buffer streaming kernel: one pixel in / one pixel out per clock.
Shift-add operators only, so 0 DSP slices, 2 BRAMs, and ~1% of the fabric.
Timing closed with margin; ~0.44 W on-chip, no soft-CPU and no AXI.

Vitis HLS Artix-7 II=1 HDMI Verilog

P-CNN · 2025 Completed

CNN Digit Detector

Full PyTorch-to-FPGA pipeline that trains a 2D CNN on an 8×8 digits dataset, exports fixed-point weights, synthesises via Vitis HLS, and displays live digit recognition over HDMI.

Conv–ReLU–MaxPool–FC pipeline at II=1, 200 MHz.
ap_fixed<16,6> arithmetic; weights baked as ROM constants.
Live HDMI display with per-class logit bar chart.

Vitis HLS CNN Artix-7 HDMI Fixed-Point

Hardware setup of the FPGA Adder showing the PA-StarLite board and LCD

P-05 · May 2026 Completed

Interactive FPGA Adder

Interactive 4-bit accumulator implemented in Verilog HDL on the PA-StarLite board, featuring debounced button control, a custom dynamic I2C LCD driver, and real-time UART logging.

Three-state accumulator FSM (Num1 Entry, Num2 Entry, and Result calculation).
Custom Verilog I2C master controller driving a 16×2 character LCD screen.
UART telemetry interface log outputs to PuTTY console at 115200 baud.

FPGA Verilog I2C LCD UART FSM

Toolchain

AMD Vivado Suite	End-to-end FPGA design covering RTL, synthesis, implementation, and timing closure.
Vitis HLS	High-level synthesis from C/C++ to optimised RTL.
Artix-7 XC7A200T	Target silicon with 215 K LUTs, 740 DSP slices, and 13 Mb BRAM.